`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/26 22:13:25
// Design Name: 
// Module Name: D_E
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "defines.vh"

module D_E(
    input logic                 clk,res,
    input logic                 en,
    input logic                 clr,

    input  logic [31: 0]        pc_d,
    input  logic                memtoreg_d,
    input  logic                memwrite_d,
    input  logic                alusrc_d,
    input  logic [ 1: 0]        regdst_d,
    input  logic                regwrite_d,
    input  logic [ 4: 0]        alucontrol_d,
    input  logic [31: 0]        read_rs_d,
    input  logic [31: 0]        read_rt_d,
    input  logic [31: 0]        read_rd_d,
    input  logic [ 4: 0]        rs_d,
    input  logic [ 4: 0]        rt_d,
    input  logic [ 4: 0]        rd_d,
    input  logic [ 4: 0]        sa_d,
    input  logic [31: 0]        data_32bits_d,
    input  logic                mduen_d,
    input  logic [ 2: 0]        cp0_sel_d,
    input  logic [ 3: 0]        store_sel_d,
    input  logic [ 3: 0]        load_type_d,
    input  logic                res_src_d,
    input  logic [`EXCS_BUS]    excs_d,
    input  logic                next_is_slot_d,
    input  logic                inslot_d,

    output logic [31: 0]        pc_e,
    output logic                memtoreg_e,
    output logic                memwrite_e,
    output logic                alusrc_e,
    output logic [ 1: 0]        regdst_e,
    output logic                regwrite_e,
    output logic [ 4: 0]        alucontrol_e,
    output logic [31: 0]        read_rs_e,
    output logic [31: 0]        read_rt_e,
    output logic [31: 0]        read_rd_e,
    output logic [ 4: 0]        rs_e,
    output logic [ 4: 0]        rt_e,
    output logic [ 4: 0]        rd_e,
    output logic [ 4: 0]        sa_e,
    output logic [31: 0]        data_32bits_e,
    output logic                mduen_e,
    output logic [2:0]          cp0_sel_e,
    output logic [3:0]          store_sel_e,
    output logic [3:0]          load_type_e,
    output logic                res_src_e,
    output logic [`EXCS_BUS]    excs_e,
    output logic                next_is_slot_e,
    output logic                inslot_e
    );

    always @(posedge clk,posedge res) begin 
        if (res) begin
            pc_e            <= 32'b0;
            memtoreg_e      <= 1'b0;
            memwrite_e      <= 1'b0;
            alusrc_e        <= 1'b0;
            regdst_e        <= 1'b0;
            regwrite_e      <= 1'b0;
            alucontrol_e    <= 3'b0;
            read_rs_e       <= 32'b0;
            read_rt_e       <= 32'b0;
            read_rd_e       <= 32'b0;
            rs_e            <= 5'b0;
            rt_e            <= 5'b0;
            rd_e            <= 5'b0;
            sa_e            <= 5'b0;
            data_32bits_e   <= 32'b0;
            mduen_e         <= 1'b0;
            cp0_sel_e       <= 3'b0;
            store_sel_e     <= 4'b0;
            load_type_e     <= 4'b0;
            res_src_e       <= 1'b0;
            excs_e          <= 0;
            next_is_slot_e  <= 1'b0;
            inslot_e        <= 1'b0;
        end 
        else if (clr) begin
            pc_e            <= 32'b0;
            memtoreg_e      <= 1'b0;
            memwrite_e      <= 1'b0;
            alusrc_e        <= 1'b0;
            regdst_e        <= 1'b0;
            regwrite_e      <= 1'b0;
            alucontrol_e    <= 3'b0;
            read_rs_e       <= 32'b0;
            read_rt_e       <= 32'b0;
            read_rd_e       <= 32'b0;
            rs_e            <= 5'b0;
            rt_e            <= 5'b0;
            rd_e            <= 5'b0;
            sa_e            <= 5'b0;
            data_32bits_e   <= 32'b0;
            mduen_e         <= 1'b0;
            cp0_sel_e       <= 3'b0;
            store_sel_e     <= 4'b0;
            load_type_e     <= 4'b0;
            res_src_e       <= 1'b0;
            excs_e          <= 0;
            next_is_slot_e  <= 1'b0;
            inslot_e        <= 1'b0;
        end 
        else if (en) begin
            pc_e            <= pc_d;
            memtoreg_e      <= memtoreg_d;
            memwrite_e      <= memwrite_d;
            alusrc_e        <= alusrc_d;
            regdst_e        <= regdst_d;
            regwrite_e      <= regwrite_d;
            alucontrol_e    <= alucontrol_d;
            read_rs_e       <= read_rs_d;
            read_rt_e       <= read_rt_d;
            read_rd_e       <= read_rd_d;
            rs_e            <= rs_d;
            rt_e            <= rt_d;
            rd_e            <= rd_d;
            sa_e            <= sa_d;
            data_32bits_e   <= data_32bits_d;
            mduen_e         <= mduen_d;
            cp0_sel_e       <= cp0_sel_d;
            store_sel_e     <= store_sel_d;
            load_type_e     <= load_type_d;
            res_src_e       <= res_src_d;
            excs_e          <= excs_d;
            next_is_slot_e  <= next_is_slot_d;
            inslot_e        <= inslot_d;
        end

        
    end
endmodule
